1. Technical Field
The present disclosure relates to semiconductor microelectronics and, more particularly, to test hardware probes, space transformers and structures, and test methods which enable test and burn-in for semiconductor wafers, die, die stacks or other semiconductor and packaging hardware.
2. Discussion of Related Art
Semiconductor chips and wafers support an increasing number of transistors as each new generation of semiconductor technology leverages the ability to use smaller device feature sizes produced from more advanced lithography. Advances in semiconductor technology have contributed to the reduction in the size and cost of chips and helped to improve cost-effective semiconductor devices. To take advantage of the semiconductor feature size reduction, the number of input/output (I/O) connections that are needed to support power, ground and signal interconnections may increase, which may require an increase in I/O interconnection density for each chip or die.
In the case of memory die, peripheral connections may be made around the perimeter of the die. In the case of processor chips, often area array connections are made across the bottom surface of a die. In addition to the advancing need for increased I/O to test chips and wafers, new applications utilizing through silicon connections for stacked die and wafers are emerging and further driving the need for enhanced I/O interconnection, as well as the need to be able to test these advanced die, wafers, stacked chips or stacked wafers.
Existing solutions for testing die and wafers include using ceramic probes, wirebond probes or thin film probes to test die with perimeter I/O or area I/O. Feature sizes for perimeter I/O are typically used in industry leading wirebond tools that are used to later connect the chips to a package where I/O count at the perimeter of the chip may be up to a few hundred I/O (typically <<1000 I/O) and with a pad to pad I/O pitch on the order of 30 to 50 microns minimum pitch. For area array interconnections, die typically have a minimum of 150 to 200 micron pad-to-pad or bump-to-bump interconnection pitch. Solutions in development may have an area array of 150 micron pad-to-pad or bump-to-bump interconnection pitch with the number of I/O on the order of a few thousand 110 (typically <<5,000 I/O). Thus, depending on chip or wafer test needs, interconnection test probes may have from tens of contacts to a few hundreds of contacts or even to a few thousand connections, which support power and ground but are typically limited to under 512 signal I/O, which may be stated as 102 connections per centimeter squared to 103 connections per centimeter squared.
A thin interface probe has been developed for making interconnection to pads or bumps where a flexible membrane with an array of electrode probe tips is used to contact an array of bumps or pads. Although this technology is utilized for area array contacts and to penetrate a bump or pad for electrical test, since it does not scale to very small scale pitch area pad and bump contacts while maintaining dimensional stability at both time zero for testing and throughout the life of testing, it does not lend itself to the dense arrays of pads and bumps.
One type or category of probe is known as a “Cobra Probe”. The Cobra Probe includes a plurality of wires that are mounted in parallel with their ends ending in a plane that is traverse to the axis of wires, such that the wire ends facilitate probing. Each wire is rigid enough to apply pressure, and the mechanical assembly of the wires can provide testing but is limited due to capacitance and inductance as well as center-to-center pitch of probe contacts to test an array or pads and/or bumps.
A probe referred to as a “Buckling Beam Probe” has probes which buckle under an axial load to provide load against pads or bumps. The performance of Buckling Beam Probes is limited due to capacitance, inductance and pitch spacing to pads and/or bumps.
A probe card has an electrically conductive probe assembly array of radiating contact tips. Probe cards have limited probe density.
Contact structures, which can support perimeter pad connections and array connections to pads or bumps at a large spacing while maintaining springable shape, have been developed but have limitations in pitch and electrical parasitics which limit its use.
A need exists for test probes and burn-in probes or sockets that can make contact to fine pitch area array and fine pitch perimeter I/O, die stacks, wafers, die, packages and microelectronic hardware.